The automated design of structures such as robotic structures, car assemblies, and circuit topologies has attracted much attention in the evolutionary computation literature, in part because evolutionary algorithms (EAs) handle non-vector search spaces of structural design problems more naturally than classical optimization algorithms. Of the various possible problems that can be studied through EAs, analog circuit design is an effective “fruitfly” for testing EA synthesis approaches for a number of reasons. First, it has current and future industrial relevance, being a field within the massive semiconductor industry and having a continuous stream of design challenges due to changing semiconductor processes and performance requirements. Second, candidate circuit designs can be evaluated, to an extent, using readily available simulators. Third, there can be several constraints and objectives to which the circuit design is subjected. Also, there may be robustness issues, such as handling environmental factors, manufacturing variation, etc. Further, topology design is considered a creative endeavor: designers refer to themselves as “artists”, and new topologies are often published in the scientific literature and/or patented. The combination of these characteristics makes analog circuit design a relevant, challenging application domain for testing EA approaches to structural synthesis.
Many EA approaches of the last decade use variants of genetic programming (GP) to search across unstructured combinations of circuit devices to “invent” circuit structures (i.e., topologies) on the fly, from scratch. Unfortunately, they have to reinvent every circuit structure, despite there being a large set of well-known analog circuit building blocks. If this were automotive design, every run would be literally reinventing the wheels, the transmission, the pistons, the chassis, etc. Furthermore, even if well-known building blocks are appropriate, there is no guarantee that those blocks will be used in order to solve the problem at hand because they will all have to be reinvented on the fly. The authors T. R. Dastidar et al, in “A Synthesis System for Analog Circuits Based on Evolutionary Search and Topological Reuse,” IEEE Trans. Ev. Comp. 9(2), April 2005, pp. 211-224 partially overcome this by supplying loosely grouped building blocks for possible use by the system. Unfortunately, this and other past EAs has a tendency to exploit missing goals to return circuits with odd structures or behavior. This is a major issue because one must trust the topology sufficiently to commit millions of dollars to fabricate and test the design. Up-front constraints such as current-mode analysis and Kirchoff's-Law constraints can be added, but plugging such “holes in goals” is tedious and provides no guarantee that the circuit returned to the designer will be trustworthy enough to send for fabrication.
Furthermore, open-ended approach makes EAs extremely computationally intensive, taking weeks or more CPU time to produce an output. Faster CPUs may not solve this because the problem itself is “Anti-Mooreware”. That is, as Moore's Law progresses, more issues, such as process variation must be handled, causing higher simulation effort.
The computer-aided design (CAD) literature has approached the analog synthesis problem in different ways. Some approaches such as, for example, BLADES, OASYS, and ISAID pre-define rule-based reasoning or abstract models having transforms to well-known structural descriptions to give trusted topologies, but unfortunately require an up-front setup effort of weeks to months, which must be repeated for each circuit type and each new process node. Other approaches such as, for example, DARWIN and MINLP also give trustworthy circuits by predefining a space of designer-known circuit topologies within a fixed-length vector, where variables enable/disable/choose components. Unfortunately the approaches rely on a sneaky definition of the search space specific to the circuit type. These methods cannot be generalized are restricted to few topologies (e.g., less than 100 topologies).
In addition to the synthesis problems of trust, runtime, setup effort, and generality, past approaches had little emphasis on giving insight back to the designer. While some expert knowledge transfers easily (e.g., building blocks), more specific knowledge such as how topologies relate to specific performance values is hard to keep up-to-date due to changing fabrication processes, requirements, etc. By relying too much on a synthesis tool, the designer could end up poorly equipped when problems arise, such as, for example a previously unseen process issue, e.g., proximity effects.
Further, as Moore's Law captures, the minimum size of transistors in integrated circuits has been decreasing at an exponential rate for several decades. For digital design, the incentive to shrink geometries is high: it means simultaneously smaller area, higher speed, and lower power. However, scaling is less beneficial to analog circuits because mismatch, which limits performance of many analog circuits, worsens as geometries shrink. To cope with mismatch, analog designers can increase device area, use many circuit-level techniques like feedback and differential design, and more recently, shift functionality to digital, and apply calibration. But these approaches only partially scale with Moore's Law because large analog-sized transistors must form the core signal path. As a result, the analog portion of mixed-signal chips risks dominating area. There is a further concern: these approaches all start with a circuit that performs well nominally, then adapt, tune or average out the variation caused by mismatch. While this is reasonable, some fear that analog design will hit a brick wall when there is simply too much process variation to tune around. To illustrate, one can take an example of a gate oxide layer having a thickness of three atoms: one or a few atoms out of place can significantly affect performance.
The design/choice of a cell-level analog circuit topology can have a giant impact on the performance of a system. Currently, industrial topology design is done almost exclusively by hand. A longtime goal has been to automate the design or choice of topology, and there has been significant progress towards the goal via the fields of evolvable hardware (EH) and analog computer-aided design (CAD), but it has not been fully realized because either the synthesized topology has not been sufficiently trustworthy, or the approach does not allow novel functionality and topologies.
Table A shows synthesis approaches, by capability. “Novel functionality” is to be understood as meaning that the approach can be set to a new problem just by changing testbenches, which allows for new types of analog circuit functionality. “Novel structures” is to be understood as meaning that the approach may invent new structures. “Trustworthy” is to be understood as meaning that the results are either designer-trusted by construction, or the new structural novelty is easily identifiable by a designer. “Topology variety” is to be understood as meaning that a set of possible topologies is sufficiently rich that it contains appropriate solution(s) to the target functionality, including problem variants with different objectives and constraint settings. “Reasonable CPU effort” is to be understood in the context of industrial use by a tool user (e.g., a semiconductor company).
Earlier EH research (row 1, Table A) focused on fully open-ended structural synthesis. However, the CPU effort was prohibitive in those approaches, and the results were not only untrustworthy—they often look strange. More recent efforts (row 2, Table A) added domain knowledge to improve efficiency and trustworthiness, but there is still no guarantee of trustworthy results or of trackable novelty.
Early CAD research (row 3, Table A) focused on searching through sets of known topologies, which gave both speed and trustworthy results; unfortunately the number of possible topologies was extremely limited and there was no clear way to generalize the approaches to more problem types. More recent research (rows 4 and 5, Table A) has attempted to merge ideas from both fields: multi-topology and multi-objective searches through combinations of hierarchically-organized designer-specified analog building blocks, thus giving a large set of topologies that can be readily applied to common analog design problems. The entry at row 5, allows for more open-ended structural novelty, but tracking the novelty explicitly and only rewarding novel individuals that actually improve performance. However, both the entries of rows 4 and 5 are constrained to problems that analog designers have attacked; they do not address problems with novel functionality.
TABLE ATopology Synthesis ApproachReasonableNovelNovelTrust-TopologyCPUApproachfunctionality?structures?worthy?variety?effort?J. R. Koza et al. Genetic Programming IV:yesyesnoyesnoRoutine Human-Competitive MachineIntelligence. Kluwer (2003)Lohn, J. D, Colombano, S. P. AutomatedAnalog Circuit Synthesis using a LinearRepresentation. Proc. ICES (1998) 125-133Shibata, H. et al.: Automated design ofanalog circuits using cell-based structure.Proc. Nasa/DoD Conf. Evolv. Hardware(2002)Sripramong, T., Toumazou, C.: TheyesyesnoyesborderlineInvention of CMOS Amplifiers UsingGenetic Programming and Current-FlowAnalysis. IEEE Trans. CAD 21(11)(2002) 1237-1252Dastidar, T. R. Chakrabarti, P. P., Ray, P.:A Synthesis System for Analog CircuitsBased on Evolutionary Search andTopological Reuse. IEEE Trans. EC 9(2)(April 2005) 211-224Mattiussi, C., Floreano, D.: AnalogGenetic Encoding for the Evolution ofCircuits and Networks. IEEE Trans. EC11(5) (2007) 596-607Kruiskamp, W., Leenaerts, D.: DARWIN:nonoyesnoyesCMOS Opamp Synthesis by Means of aGenetic Algorithm. Proc. DAC (1995)433-438Maulik, P., Carley, L., Rutenbar, R. A.:Integer Programming Based TopologySelection of Cell Level Analog Circuits.IEEE Trans. CAD 14(4) (April 1995) 401-412McConaghy, T., Palmers, P., Gielen, G.,nonoyesyesyesand Steyaert, M.: Simultaneous multi-topology multi-objective sizing acrossthousands of analog circuit topologies.Proc. DAC (2007) 944-947McConaghy, T., Palmers, P., Gielen, G.,noyesyesyesyesand Steyaert, M.: Genetic programmingwith design reuse for industriallyscalable, novel circuit design. GP Theoryand Practice V, Springer (2007) 159-184
Therefore, it is desirable to provide a method of designing analog circuits that is naturally robust to variations without needing tuning and yet scales with Moore's Law, i.e., uses the smallest possible transistors. It is also desirable to provide a method of designing analog circuits that have trustworthy topologies and to provide a method of extracting knowledge from the trustworthy topologies in order to provide insight to the designer.